Silicon economics · 300 mm wafer
Die Yield & Cost Calculator
See what each good die really costs — and whether splitting a reticle-class design into 2, 4, or 8 chiplets changes the silicon math.
The largest area a standard scanner exposes in one step. Past this line, large designs usually need stitching.
Wafer model
Price the die, then test the split
Fits within one standard exposure field.
Cost per good die
$607.14
47.4% predicted yield · $17,000 wafer
Predicted yield
47.4%
Murphy model
Gross dies
61
Per 300 mm wafer
Good dies
28
After yield
Good silicon
$0.759
Per good mm²
Splitting into 8 equal 100 mm² chiplets gives the lowest modeled silicon cost per equivalent package.
8-chip split · −60%Monolithic vs. chiplet split
Same total silicon area, divided into equal chiplet counts.
| Split | Area/chip | Yield | Good/wafer | $/package |
|---|---|---|---|---|
| 1×mono | 800 mm² | 47.4% | 28 | $607 |
| 2× | 400 mm² | 67.9% | 93 | $366 |
| 4× | 200 mm² | 82.1% | 240 | $283 |
| 8× | 100 mm² | 90.6% | 555 | $245 |
Scope: silicon cost only. Assembly, interposer, test, package yield, and the engineering cost of disaggregation are excluded — small chiplets can look cheaper here while costing more in total.
How it works
From wafer price to a design decision
Three inputs. Four split scenarios. One clear cost signal.
Set the silicon
Enter total design area, defect density, and the processed 300 mm wafer cost. Area is converted to cm² before yield math.
Read the real cost
Murphy yield and wafer geometry produce gross dies, good dies, and the cost of one working die — plus cost per good mm².
Test the split
The same total area is divided into 2, 4, and 8 chiplets. The table prices enough good chips to make one equivalent package.
What is modeled
Murphy's yield curve is Y = ((1 − e−A·D0) / (A·D0))², where A is die area in cm². It is a useful planning approximation, not a fab-specific forecast.
Wafer geometry
Gross die count uses the classic circular-wafer approximation with a 147 mm usable radius — a 300 mm wafer after 3 mm edge exclusion. Real layouts, scribe lines, and die shapes cause variation.
Chiplet comparison
Each chiplet is assumed identical, has the same D0, and is independently yielded. Package silicon cost is wafer cost divided by good chips available per package. Assembly and package yield are outside this number.
FAQ
Silicon math, without the mystery
Why does yield fall so fast for big dies?+
Yield depends on die area multiplied by defect density. A larger die collects more defects, and the Murphy curve compounds that effect. Doubling area does not simply halve the good-die count.
Why is gross die count an approximation?+
The circular-wafer formula estimates packing without modeling the exact die aspect ratio, scribe lanes, or edge exclusion pattern. Use it for orientation and scenario comparison, not a guaranteed wafer map.
Does a cheaper chiplet split include packaging?+
No. The comparison isolates silicon economics. Advanced packaging, interposers, assembly yield, test, and design partitioning can erase the savings shown here — especially as chiplet count rises.
What changes above 858 mm²?+
A standard reticle field is 26 × 33 mm, or 858 mm². Larger designs need stitching or multiple die. This calculator keeps the area-based estimate so you can see the cost pressure, but flags the reticle limit.